In the fabrication of semiconductor integrated circuits, metal conductor lines are used to interconnect the multiple components in device circuits on a semiconductor wafer. A general process used in the deposition of metal conductor line patterns on semiconductor wafers includes deposition of a conducting layer on the silicon wafer substrate; formation of a photoresist or other mask such as titanium oxide or silicon oxide, in the form of the desired metal conductor line pattern, using standard lithographic techniques; subjecting the wafer substrate to a dry etching process to remove the conducting layer from the areas not covered by the mask, thereby leaving the metal layer in the form of the masked conductor line pattern; and removing the mask layer typically using reactive plasma and chlorine gas, thereby exposing the top surface of the metal conductor lines. Typically, multiple alternating layers of electrically conductive and insulative materials are sequentially deposited on the wafer substrate, and conductive layers at different levels on the wafer may be electrically connected to each other by etching vias, or openings, in the insulative layers and filling the vias using aluminum, tungsten or other metal to establish electrical connection between the conductive layers.
A current drive in the semiconductor device industry is to produce semiconductors having an increasingly large density of integrated circuits which are ever-decreasing in size. These goals are achieved by scaling down the size of the circuit features in both the lateral and vertical dimensions. Vertical downscaling requires that the thickness of gate oxides on the wafer be reduced by a degree which corresponds to shrinkage of the circuit features in the lateral dimension. While there are still circumstances in which thicker gate dielectrics on a wafer are useful, such as to maintain operating voltage compatibility between the device circuits manufactured on a wafer and the current packaged integrated circuits which operate at a standard voltage, ultrathin gate dielectrics will become increasingly essential for the fabrication of semiconductor integrated circuits in the burgeoning small/fast device technology.
The ongoing advances in the field of fabricating miniaturized electronic integrated circuits (ICs) has involved the fabrication of multiple layers of interconnects, or the layers of separate electrical conductors which are formed on top of a substrate and connect various functional components of the substrate and other electrical connections to the IC. Electrical connections between the interconnect layers and the functional components on the substrate are achieved by via interconnects, which are post- or plug-like vertical connections between the conductors of the interconnect layers and the substrate. ICs often have five or more interconnect layers formed on top of the substrate.
Capacitors are one of the most common passive elements used in very large-scale integrated (VLSI) circuits. Capacitors are often integrated into active elements such as bipolar transistors or complementary metal oxide semiconductors (CMOS) transistors. Capacitors in semiconductor devices may have one of various forms, including polysilicon-insulator-polysilicon (PIP), metal-insulator-silicon (MIS), metal-insulator-metal (MIM) and metal-insulator-polysilicon (MIP).
A conventional MIP (Metal-Insulator-Polysilicon) capacitor structure 10 is shown in FIG. 1. The MIP capacitor structure 10 includes a polysilicon layer 12, a first dielectric layer 14 provided on the polysilicon layer 12, a second dielectric layer 16 provided on the first dielectric layer 14 and a metal layer 18 provided on the second dielectric layer 16. As shown in FIG. 1, the area of the dielectric layers 14, 16 is the same as the area of the metal layer 18. Thus, the edges 20 of the dielectric layers 14, 16 are flush with the edges 19 of the metal layer 18.
The capacitance (C) of the MIP capacitor structure 10 is a function of the dielectric film area (A) and the dielectric film thickness (d), according to the following equation: C=εA/d. The electrical charge (Q) established across the structure 10 is related to the capacitance (C) and voltage (V) differential according to the equation Q=CV. Therefore, increasing the area or decreasing the thickness of the dielectric layers 14, 16 correspondingly increases the capacitance, and thus, the charge established across the dielectric layers 14, 16 of the capacitor structure 10.
During application of an electrical charge (Q) across the first dielectric layer 14 and the second dielectric layer 16, the strength of the electric field 22 at the dielectric layer edges 20 and at the center region of the dielectric layers 14, 16 is non-uniform. This results in breakdown of the dielectric layers 14, 16 at the dielectric layer edges 20, causing electrical shorting of the capacitor structure 10. In MIP capacitor structures, the roughness of the polysilicon surface further contributes to breakdown of the dielectric layer or layers.
It is believed that optimizing the profile of a capacitor structure in such a manner that the area of the dielectric layer or layers is larger than the area of the metal or polysilicon layer facilitates formation of an electric field which is substantially uniform across all regions of the dielectric layer or layers. This prevents or substantially reduces breakdown of the dielectric layer edges of the capacitor structure.
Accordingly, an object of the present invention is to provide a novel, pyramid-shaped structure for a capacitor.
Another object of the present invention is to provide a novel capacitor structure which has a generally stepped profile to prevent or substantially reduce breakdown of the edges of a dielectric layer or layers.
Still another object of the present invention is to provide a novel capacitor structure which is applicable to an MIP (Metal-Insulator-Polysilicon) or a PIP (Polysilicon-Insulator-Polysilicon) capacitor structure.
Yet another object of the present invention is to provide a novel, generally pyramidal or stepped profile capacitor structure in which an electrically-insulating dielectric layer sandwiched between a metal layer and a polysilicon layer has an area which is larger than the area of the metal layer.
A still further object of the present invention is to provide a novel method of fabricating a capacitor structure having a generally pyramidal or stepped profile to prevent or substantially reduce the incidence of dielectric layer breakdown at the edges of a dielectric layer or layer sandwiched between a polysilicon layer and a metal layer or between two polysilicon layers.